Gate signal line drive circuit and display
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United States of America Patent
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Oct 20, 2015
Grant Date -
Oct 16, 2014
app pub date -
Apr 11, 2014
filing date -
Apr 12, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A gate signal line drive circuit and a display using the circuit, which suppress a leak current to reduce a power consumption. A gate signal line drive circuit that supplies a high voltage in a signal high period, and supplies a low voltage in a signal low period, the gate signal line drive circuit including: a high voltage supply switching element that turns on in response to the high period, supplies a voltage of a first basic clock signal to gate signal lines; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines in response to the signal low period.
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