Techniques for reducing disturbance in a semiconductor memory device
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United States of America Patent
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Nov 7, 2017
Grant Date -
Oct 16, 2014
app pub date -
Jun 24, 2014
filing date -
Nov 24, 2009
priority date (Note) -
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Abstract
Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.
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