Through-vias for wiring layers of semicondutor devices
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United States of America Patent
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Jan 12, 2016
Grant Date -
Oct 23, 2014
app pub date -
Aug 20, 2013
filing date -
Apr 18, 2013
priority date (Note) -
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Abstract
Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining.
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