High-Speed Current Steering Logic Output Buffer
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United States of America Patent
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app pub date -
May 21, 2013
filing date -
Apr 19, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.
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