METHODS OF FORMING ISOLATION REGIONS FOR BULK FINFET SEMICONDUCTOR DEVICES
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United States of America Patent
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Issued Date -
Oct 23, 2014
app pub date -
Apr 17, 2013
filing date -
Apr 17, 2013
priority date (Note) -
Abandoned
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Abstract
One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.
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