Implementing ECC redundancy using reconfigurable logic blocks
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United States of America Patent
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Jan 5, 2016
Grant Date -
Oct 23, 2014
app pub date -
Apr 22, 2013
filing date -
Apr 22, 2013
priority date (Note) -
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Abstract
A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
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