DUAL SHALLOW TRENCH ISOLATION (STI) FIELD EFFECT TRANSISTOR (FET) AND METHODS OF FORMING
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United States of America Patent
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Issued Date -
Nov 6, 2014
app pub date -
May 1, 2013
filing date -
May 1, 2013
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Abandoned
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Abstract
Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
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