Integrated circuit with toggle suppression logic
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United States of America Patent
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Nov 10, 2015
Grant Date -
Nov 6, 2014
app pub date -
Jun 7, 2013
filing date -
May 6, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal. The integrated circuit includes a switching element configured to receive the first enable signal and the second enable signal to generate a third enable signal. The integrated circuit includes combinational logic coupled to the loading circuit and the switching element, in which the combinational logic is configured to receive the third enable signal. The third enable signal is configured to disable toggling in the combinational logic while the loading circuit operates in the shift mode.
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