Margin test methods and circuits

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United States of America Patent

PATENT NO 9116810
APP PUB NO 20140331112A1
SERIAL NO

14333665

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fred F San Francisco, US 70 1457
Garlepp, Bruno W Sunnyvale, US 89 3410
Ho, Andrew Menlo Park, US 50 1901
Stojanovic, Vladimir Lexington, US 66 343

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