Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance
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United States of America Patent
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Feb 17, 2015
Grant Date -
Nov 13, 2014
app pub date -
Jul 24, 2014
filing date -
Mar 23, 2012
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Abstract
A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance.
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