Semiconductor package comprising stacked integrated circuit chips having connection terminals and through electrodes symmetrically arranged
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United States of America Patent
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Nov 21, 2017
Grant Date -
Nov 13, 2014
app pub date -
May 5, 2014
filing date -
May 10, 2013
priority date (Note) -
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Abstract
An integrated circuit device comprises N stacked first integrated circuit chips each of which includes a first circuit and N stacked second integrated circuit chips each of which includes a second circuit. The N stacked second integrated circuit chips are stacked on the N stacked first integrated circuit chips. A first and second integrated circuit chips at symmetric positions with respect to a reference surface are paired. Each of the first and second integrated circuit chips include connection terminals for connecting the first circuit of the first integrated circuit chip and the second circuit of the second integrated circuit chip in the pair, and through electrodes each penetrating an inside of the chip. The connection terminals and through electrodes are arranged to be symmetric with respect to the reference surface.
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