Write level training using dual frequencies in a double data-rate memory device interface
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United States of America Patent
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Jan 20, 2015
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May 9, 2013
filing date -
May 9, 2013
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Abstract
A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.
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