Memory device and method of controlling memory device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 3, 2015
Grant Date -
Nov 20, 2014
app pub date -
Sep 12, 2013
filing date -
May 14, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit executing a write/erase of at least one of the resistance change elements, and executing a recovering operation which adjusts a threshold voltage shift of the select FET after the write/erase.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully