CURRENT-LIMITING LAYER AND A CURRENT-REDUCING LAYER IN A MEMORY DEVICE
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United States of America Patent
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Issued Date -
Dec 4, 2014
app pub date -
Aug 13, 2014
filing date -
Jul 29, 2011
priority date (Note) -
Abandoned
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Abstract
A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.
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