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United States of America Patent
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Issued Date -
Dec 4, 2014
app pub date -
Feb 25, 2014
filing date -
May 30, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out on the strings, the first value for a first string being updated when a read or write operation is carried out on a memory cell transistor of the first string and the second value being updated when a read or write operation is carried out on a memory cell transistor of a second string that is different from the first string.
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