Hierarchical design of integrated circuits with multi-patterning requirements

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9348962
APP PUB NO 20140359547A1
SERIAL NO

14463025

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Abstract

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Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Buck, Nathan Underhill, US 16 75
Dreibelbis, Brian Underhill, US 9 62
Dubuque, John P Jericho, US 27 266
Foreman, Eric A Fairfax, US 85 747
Hathaway, David J Underhill, US 117 1970
Hemmett, Jeffrey G St. George, US 55 459
Venkateswaran, Natesan Hopewell Junction, US 56 421
Visweswariah, Chandramouli Croton-on-Hudson, US 112 1855
Zolotov, Vladimir Putnam Valley, US 80 1100

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