Memory devices and memory operational methods including single erase operation of conductive bridge memory cells
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United States of America Patent
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May 24, 2016
Grant Date -
Dec 11, 2014
app pub date -
Jun 10, 2013
filing date -
Jun 10, 2013
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Abstract
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
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