Non-volatile FINFET memory array and manufacturing method thereof
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United States of America Patent
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Jun 21, 2016
Grant Date -
Dec 18, 2014
app pub date -
Oct 11, 2013
filing date -
Jan 13, 2011
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Abstract
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
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