Pulsed-latch based razor with 1-cycle error recovery scheme

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United States of America Patent

PATENT NO 9009545
SERIAL NO

13918587

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Abstract

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Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Jae-Joon Pohang, KR 75 573
Lin, Yu-Shiang Elmsford, US 14 74
Shin, Insup Daejeon, KR 7 14

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