Methods and apparatus for an ISFET

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United States of America Patent

PATENT NO 9599587
SERIAL NO

14478149

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Abstract

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An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

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Patent Owner(s)

  • NXP USA, INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Weize Phoenix, US 57 443
De, Souza Richard J Chandler, US 33 330
Hoque, Md M Gilbert, US 13 137
McKenna, John M Chandler, US 10 212
Parris, Patrice M Phoenix, US 62 541

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