Method to increase I/O density and reduce layer counts in BBUL packages
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United States of America Patent
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May 26, 2015
Grant Date -
Jan 1, 2015
app pub date -
Jun 28, 2013
filing date -
Jun 28, 2013
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Abstract
An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- INTEL CORPORATION
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Agraharam, Sairam | Chandler, US | 59 | 284 |
Raorane, Digvijay A | Chandler, US | 32 | 254 |
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