MULTIPATTERNING VIA SHRINK METHOD USING ALD SPACER
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United States of America Patent
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Issued Date -
Jan 1, 2015
app pub date -
Jun 30, 2014
filing date -
Jun 28, 2013
priority date (Note) -
Abandoned
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Abstract
A method of manufacturing a semiconductor device an include forming an first low temperature oxide (LTO) layer over an organic planarization layer (OPL) layer, forming a primary via pattern in the LTO layer to partially expose the OPL layer, forming a conformal second LTO layer over the primary via pattern including the first LTO layer and the partially exposed OPL layer, and etching the second LTO layer to form spacers on sidewalls of the primary via pattern in the first LTO layer.
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