Master/slave control voltage buffering

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United States of America Patent

PATENT NO 9754656
SERIAL NO

13929967

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Abstract

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In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Spinks, Stephen J Swindon, GB 5 32

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