MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE
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United States of America Patent
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Issued Date -
Jan 1, 2015
app pub date -
Sep 15, 2014
filing date -
Jan 13, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A memory device can include a memory array configured to store a first plurality of bits and a second plurality of bits. The memory device may include an address port configured to receive at least a portion of a first address associated with a first command during a first clock cycle, and at least a portion of a second address associated with a second command during the first clock cycle. The memory device may include a plurality of data ports that includes a first data port configured to access the first plurality of bits in response to the receiving of the at least a portion of the first address during the first clock cycle, and a second data port configured to access the second plurality of bits in response to the receiving of the at least a portion of the second address during the first clock cycle.
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