Device packaging with substrates having embedded lines and metal defined pads

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United States of America Patent

PATENT NO 9093313
APP PUB NO 20150008578A1
SERIAL NO

14481766

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Abstract

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Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hlad, Mark S Chandler, US 14 118
Lee, Kyu Oh Chandler, US 56 227
Liu, Yueli Gilbert, US 18 148
Roy, Mihir K Chandler, US 60 451
Salama, Islam A Chandler, US 64 448
Wu, Tao Chandler, US 348 4132

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