Method and apparatus for reducing read latency
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United States of America Patent
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Jan 10, 2017
Grant Date -
Jan 15, 2015
app pub date -
Sep 2, 2014
filing date -
Mar 30, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.
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