Early data delivery prior to error detection completion
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United States of America Patent
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Aug 11, 2015
Grant Date -
Jan 15, 2015
app pub date -
Sep 30, 2014
filing date -
Mar 15, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem.
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