Erase management in memory systems
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United States of America Patent
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Nov 1, 2016
Grant Date -
Jan 22, 2015
app pub date -
Jul 16, 2013
filing date -
Jul 16, 2013
priority date (Note) -
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Abstract
Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system.
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