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Abstract

A method and apparatus for transmitting data over a clock-gated mesochronous clock domain boundary in an interconnect network of an integrated circuit. New data is received into storage buffers within a sender domain. The data is synchronized by sending time-controlled signals from storage elements in a sender control within the sender domain to corresponding inputs in a receiver control signal path in a receiver domain. Multiplexers are signaled to sequentially transmit the data from the storage buffers across the domain boundary to the receiver domain according to the time-controlled signals received from the sender control by the receiver control signal path, where the multiplexers receive signals from a data path pointer counter in communication with the receiver control signal path.

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First Claim