MULTIPLEXER, LOOK-UP TABLE AND FPGA
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United States of America Patent
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Issued Date -
Jan 29, 2015
app pub date -
Feb 11, 2013
filing date -
Mar 6, 2012
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Abstract
The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.
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