Methods and circuits for dynamically scaling DRAM power and performance
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United States of America Patent
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Feb 9, 2016
Grant Date -
Jan 29, 2015
app pub date -
Aug 5, 2014
filing date -
Feb 23, 2010
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Abstract
A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
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