Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability
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United States of America Patent
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Sep 15, 2014
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Nov 19, 2012
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Abstract
A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
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