Semiconductor memory device including refresh operations having first and second cycles
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United States of America Patent
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Oct 10, 2017
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N/A
app pub date -
Jul 30, 2014
filing date -
Jul 31, 2013
priority date (Note) -
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Abstract
Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.
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