Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
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United States of America Patent
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May 24, 2016
Grant Date -
Feb 12, 2015
app pub date -
Aug 7, 2013
filing date -
Aug 7, 2013
priority date (Note) -
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Abstract
After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.
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