Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Feb 19, 2015
app pub date -
Aug 16, 2013
filing date -
Aug 16, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A three-dimensional NAND memory device and an associated method for manufacturing this device are provided. The three-dimensional NAND memory device includes a source contact electrically isolated from a conductive gate material. The source contact also electrically connects a conductive source line to a first silicon strip and a second silicon strip through the conductive gate material.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully