Dual-port positive level sensitive reset preset data retention latch
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United States of America Patent
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Apr 28, 2015
Grant Date -
Feb 26, 2015
app pub date -
Nov 14, 2013
filing date -
Aug 26, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
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