Efficient arithimetic logic units
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United States of America Patent
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Aug 4, 2015
Grant Date -
Feb 26, 2015
app pub date -
Oct 31, 2014
filing date -
Jun 17, 2009
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Abstract
A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.
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