CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE
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United States of America Patent
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Issued Date -
Feb 26, 2015
app pub date -
Aug 21, 2013
filing date -
Aug 21, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.
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