PROGRAMMABLE MEMORY
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United States of America Patent
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Issued Date -
Mar 5, 2015
app pub date -
Apr 24, 2014
filing date -
Sep 4, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A programmable memory is provided. The programmable memory has a select transistor that includes a gate, a source, and a drain. An anti-fuse device is connected to a drain region of the select transistor. The anti-fuse device includes a dielectric layer on an upper substrate of the drain region, a polysilicon layer on the dielectric layer, and an anti-fuse electrode line in contact with the drain region. The dielectric layer breaks down and the anti-fuse device is programmed when the select transistor is turned on and a high voltage is applied through the anti-fuse line.
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