MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD
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United States of America Patent
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Issued Date -
Mar 5, 2015
app pub date -
Feb 28, 2014
filing date -
Sep 5, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
According to one embodiment, a memory controller includes an address translation information storage unit that stores plural translation information formed by classifying a correspondence between a logical address and a physical address into two or more hierarchies, a tag management unit that sores a cache line tag, which includes hierarchy information corresponding to each of the translation information stored in the translation information storage unit, and a control unit that identities whether the translation information is stored in the translation information storage unit or not by using a cache line tag.
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