Reducing latency of unified memory transactions
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United States of America Patent
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Nov 8, 2016
Grant Date -
Mar 5, 2015
app pub date -
Jun 27, 2014
filing date -
Sep 3, 2013
priority date (Note) -
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Abstract
In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.
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