Level shifter with built-in logic function for reduced delay
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United States of America Patent
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Mar 17, 2015
Grant Date -
Mar 12, 2015
app pub date -
Sep 11, 2013
filing date -
Sep 11, 2013
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Abstract
A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.
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