Semiconductor memory system including a plurality of semiconductor memory devices

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United States of America Patent

PATENT NO 9601206
SERIAL NO

14539522

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Abstract

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A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shibata, Noboru Kawasaki, JP 304 4741
Sukegawa, Hiroshi Minato-ku, JP 138 3543

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