Memory device having a stacked variable resistance layer
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United States of America Patent
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Dec 1, 2015
Grant Date -
Mar 19, 2015
app pub date -
Jul 30, 2014
filing date -
Sep 17, 2013
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Abstract
A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.
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