Memory chip, memory device, and reading method
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United States of America Patent
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Jan 10, 2017
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N/A
app pub date -
Mar 3, 2014
filing date -
Sep 13, 2013
priority date (Note) -
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Abstract
A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.
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