SONOS FPGA architecture having fast data erase and disable feature
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United States of America Patent
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Aug 11, 2015
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app pub date -
Sep 10, 2014
filing date -
Sep 25, 2013
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Abstract
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
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