Power distribution for 3D semiconductor package
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United States of America Patent
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Apr 28, 2015
Grant Date -
Apr 2, 2015
app pub date -
Sep 30, 2013
filing date -
Sep 30, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.
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