Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
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United States of America Patent
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app pub date -
Dec 10, 2014
filing date -
Apr 18, 2013
priority date (Note) -
Abandoned
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Abstract
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
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