REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS
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United States of America Patent
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Issued Date -
Apr 2, 2015
app pub date -
Oct 3, 2013
filing date -
Oct 1, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.
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