High speed, low power, isolated buffer
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United States of America Patent
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Aug 20, 2019
Grant Date -
Apr 2, 2015
app pub date -
Sep 30, 2013
filing date -
Sep 30, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.
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